The example embodiments relate to a built-in self-test (BIST) circuit, and more particularly, to a BIST circuit, a memory device including the BIST circuit, and a method of operating the BIST circuit.
As semiconductor manufacturing technology develops, integration of semiconductor devices increases and simultaneously a possibility of failure of the semiconductor device may further increase. Thus, a process of catching a problem of a semiconductor manufacturing process is desired and may be performed by analyzing a failure that occurs in the semiconductor device.
For example, a memory device has been tested by using external dedicated equipment. However, significant changes have occurred with respect to a method of testing the memory device due to the advent of system on chip (SoC) technology that forms a system in a single chip. An SoC uses a plurality of built-in memory devices having a large width data I/O for improving performance. It may be inefficient to test such built-in memory devices by using the existing dedicated test equipment due to a lack of channel numbers, a limitation of a high speed test, and low accessibility to the built-in memory devices.
As an alternative to handling the problem, a method of including a BIST circuit in an SoC has been developed. The method is often used in the high speed test compared to the method using external dedicated equipment, and thus research has been carried out thereon. At present, a BIST method is widely used as a method of testing a built-in memory device currently included in the SoC.